1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and, more particularly, to a semiconductor integrated circuit device, and a design automation method, apparatus and program which employ a test facilitating design technology.
2. Description of the Related Art
Boundary scan (JTAG) which is one scheme for test facilitating design is standardized in 1990 as described in IEEE std 1149.1-1990 Standard Test Access Port and Boundary-Scan Architecture and is a test method mainly aiming at checking wiring connection between LSIs.
FIG. 1 is a diagram illustrating the schematic structure of a typical boundary-scan circuit (see, for example, “Fundamentals and Application of JTAG Test” by Kazumi Sakamaki, p 24, FIG. 2-2, CQ Publication Co., Ltd., Dec. 1, 1998). A boundary-scan register has a multiplexer M1, a flip-flop F1, a flip-flop F2, and a multiplexer M2. The multiplexer M1 receives a serial signal input SI and a signal input PI and selects the input SI in response to a Shift_DR command (signal 5). The flip-flop F1 samples the output of the multiplexer M1 according to a shift clock and outputs a sampled signal as SO. The flip-flop F2 samples the output of the flip-flop F1 according to an update clock (Update_DR) and outputs a sampled signal. The multiplexer M2 receives the output of the flip-flop F2 and the signal PI and outputs one of the inputs to a terminal PO based on a mode signal MODE. In case of an input cell, the terminal PI is connected to the input pin and the terminal PO to an internal circuit. In case of an output cell, the terminal P1 is connected to the internal circuit and the terminal PO to the output pin. An input/output cell takes such a structure as to have two circuits each as shown in FIG. 2 which are switched from one to the other in accordance with the input and the output. The serial input terminal SI receives TDI (Test Data Input) or an output TDO (Test Data Output) of the boundary-scan circuit at the previous stage.
In the boundary-scan test, a board tester executes a board test by inputting and outputting test data in such a way as to sequentially connect shift registers inside a boundary-scannable device on a board to be tested. The signal TDI from the board tester is connected to the TDI pin of the boundary-scannable device, is output from the TDO pin of the device, and is then connected to the TDI pin of a boundary-scannable device at the next stage. The signal TDI is sequentially connected to all boundary-scannable devices on the board in this manner. The TDO pin of the last device is connected to the TDO pin of the board tester. Signals TCK and TMS from the board tester are connected to all the boundary-scannable devices in the form of a bus. The boundary-scannable device has a boundary-scan register (see FIG. 1) provided between the external I/O pin and the internal logic, and the boundary-scan register forms a scan chain between the TDI pin and the TDO pin. The boundary-scannable device has terminals TCK (test clock input terminal), TMS (test mode select input terminal), TDI (test data input terminal), TDO (test data output terminal) and TRST (test reset terminal) as external control terminals to connect the boundary-scan control circuit in the LSI to an external unit, and is controlled by signals TCK, TMS and so forth. The boundary-scannable device includes a TAP (Test Access Port) controller, which is a state machine to control the flow of a test command and data to the boundary-scan circuit, an instruction register which holds an instruction code loaded from the TDI terminal, and an instruction decoder which generates a test control signal from the instruction loaded into the instruction register. The boundary-scannable device has the boundary-scan register, a bypass register and a user definition register as data registers to be connected to the TDI terminal and TDO terminal.
FIG. 2 is a schematic diagram illustrating a typical conventional example of the layout in an ASIC (Application Specific IC) device, paying attention to I/O cells. In the example shown in FIG. 2, three types of buffers A (11), B (12) and C (13) are laid out in the layout area (called “I/O area”) between the external pins and an inner area 10 in the peripheral area of a chip 1. Each of those buffers 11, 12 and 13 has a boundary-scan cell structure including a boundary-scan register. Corner cells 14 which serve as test control circuits are provided at the four corners and a buffer 24 of each corner cell 14 enable wirings 31, 32 and 33 to transfer test signals. The wirings 31, 32 and 33 are global wirings running through the I/O cell area in the chip's peripheral portion over a plurality of I/O cells. The wirings 31, 32 and 33 are laid on a metal wiring layer on the top layer of the substrate and are connected via through holes and contacts to the gate electrodes, the drain terminals or so of elements which constitute boundary-scan circuits 21, 22, etc. in the I/O cells.
The operation of the chip shown in FIG. 2 is briefly discussed. In normal operation mode, an I/O cell serves as a buffer circuit which receives a signal applied to the input pin and supplies the signal to the internal circuit, or receives a signal from the internal circuit and outputs the signal from the output pin, or receives and outputs a signal at and from an I/O pin common to the input and output.
In test mode, the pins of the device are isolated from the internal circuit and test signals are supplied to the boundary-scan registers. Each boundary-scan register serves a shift register and outputs a signal input from the unillustrated TDI terminal to the unillustrated TDO terminal. In the example shown in FIG. 2, each I/O cell has such a structure as to include the control circuit 21, 22 or the like for the boundary-scan test and some I/O cells have buffers 23 for enabling the global wirings.
As fan-out adjustment of a test net which passes through the boundary-scan register, the following method (Japanese Patent Laid-Open No. 2002-26129) is known. According to the method, after the layout of I/O cells, I/O connection boundary-scan registers are laid out in empty areas near the I/O cells by priority before laying out an internal logic circuit or the like, an I/O control boundary-scan register is laid out at the midway point between the I/O connection boundary-scan registers or the side of the chip closer to the midway point, then buffer cells are laid out in test nets corresponding to the boundary-scan registers connected to the test control circuits before creating the layout and wiring patterns of cells which constitute other circuits, whereby fan-out adjustment between the test control circuits and the boundary-scan registers is executed with the minimum number of buffers inserted. Unlike the conventional method, the present invention inserts a buffer in an empty cell in the I/O area as will be apparent from the description of the present invention given later.
There is a design method for a signal propagation circuit which can uniquely determine the optimal circuit structure by independently determining and can facilitate the optimal design to minimize the delay time of the signal propagation circuit by independently determining the size and number of the inverters or buffers to be inserted (Japanese Patent Laid-Open No. 2001-290854).
With the structure shown in FIG. 2, however, the test circuits are arranged at the corners or so of a chip and test signals are supplied to the I/O cells from the test circuits. As the chip size increases, therefore, the wiring length becomes longer and the delay of the test signals increases because of factors, such as the wiring resistance and floating capacitance, thereby increasing the degree of waveform depression at a far end. This lowers the accuracy and reliability of the test.
Further, as the structure shown in FIG. 2 distributes the test signals from the test circuits located at the corners, delay adjustment cannot be carried out.